Each circuit on a printed wiring board is tested by applying a test signal to a first set of circuit nodes and then measuring the response at a second set of nodes, each connected to one of the first set along a circuit path. The circuit path between nodes typically includes a "net" which is defined as an equipotential surface (e.g., a metallized path on the board) which connects at least one signal transmitter ("driver") to at least one signal receiver ("receiver"). If the circuit is operating properly, i.e., the receivers and drivers are functioning properly and the nets are not shorted or open, then the response or signature of the circuit to the test signal should correspond to the test signal itself. On the other hand, if the circuit operation is faulty because two or more nets are shorted or one or more nets is open, then the circuit generates a signature which does not correspond to the test signal.
Typically, each test signal applied to the first set of circuit nodes usually takes the form of a parallel test vector comprised of n bits (ones or zeros), where n is the number of nets. Each of the bits in the test vector is applied to a separate one of the nodes in unison or parallel with the other bits, hence the reason for using the term parallel to describe the test vector. The particular sequences of the bits in the parallel test vectors is selected to reveal the shorts and opens among the nets as well as any "stuck-at" faults at the receivers or drivers. A stuck-at fault is present if the driver or receiver always produces a one or zero at its output regardless of whether a one or zero is at its inputs.
It is well known in the art that at least log (n) separate parallel test vectors are required to determine the integrity of the n nets. At least log (n+2) vectors are required if the stuck-at faults are to be detected as well. The reason for the additional two vectors is that detection of a stuck-at fault requires that both a zero and one must be applied (in sequence) to the net. A sequential test vector (as defined hereafter) which contains all zeroes or all ones will not satisfy this constraint.
A simple set of parallel test vectors, which will test the integrity of a set of n nets as well as the stuck-at faults, is given by the following matrix where each parallel test vector comprises a separate matrix column. ##STR1## Each row of the above matrix of parallel test vectors corresponds to a sequence of bits applied to each net over time. For this reason, each matrix row is often referred to as a sequential test vector. As may be appreciated, the sequential test vectors of this set monotonically increase in value; hence, the above set of parallel test vectors id described as a "counting" sequence.
The counting sequence of parallel test vectors, while compact in terms of the numbers of vectors it contains, does not afford good diagnostic capability. In other words, the response of the circuit following receipt of the parallel test vectors does not yield a good determination of which of the nets is open or shorted. In particular, the counting sequence of test vectors can give rise to two different types of incorrect responses, each defined as a "syndrome." The first type of syndrome, known as the "aliasing" syndrome, occurs when the response generated by a circuit having a faulty set of nets is the same as one having a fault-free set of nets, making it impossible to distinguish between them. The second type of syndrome is the "confounding" syndrome which occurs when the response of a circuit having only a single shorted net is the same as the response when several nets are shorted. These two syndromes are not mutually exclusive; both can occur.
The aliasing and confounding syndromes can be avoided by use of the "walking one" sequence of test vectors shown in matrix form below. ##STR2##
As with the test vector matrix which produces the counting sequence, each column in the test vector matrix which produces the walking one sequence represents a parallel test vector of n bits whereas each row represents a sequential test vector of n bits. The reason why the sequence obtained by the above matrix is described by the term "walking one" is that the "1" shifts or walks from left to right from the first to the nth sequential test vector. An important attribute of the walking one sequence of test vectors is its property of diagonal independence, i.e., the sequence of bits along the matrix diagonal is all ones. This property allows the walking one sequence to completely diagnose all faulty nets.
The disadvantage of the walking one sequence is that n, rather than log (n+2) vectors are required, making this sequence very large. As a consequence, the amount f time required for testing is increased since a larger number of vectors must be input, in sequence, to the circuit.
Thus, there is a need for a technique for generating a reasonably compact set of test vectors which provides good diagnostic capability.